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Bryan Cantrill presents the ARC (Adaptive Replacement Cache) paper by Megiddo and Modha at Papers We Love. He opens with a survey of caching strategies before digging into the self-tuning LRU/MFU design.

Cliff Click walks through a small performance example on a modern out-of-order CPU. He covers pipelining, ILP, CISC vs RISC, multicore, and why cache misses and the memory subsystem dominate performance.

Matt Godbolt builds a toy path tracer in C++ in three different styles and compares them on clarity, testability, compile time and run-time performance. The talk was given at CppCon 2019.

Gor Nishanov's CppCon 2018 talk on using tiny C++ coroutines to hide memory latency, interleaving useful work while prefetches bring cache lines in from main memory.

Netflix engineer Drew Gallatin's EuroBSDcon 2022 talk quantifies the older FreeBSD optimizations that let Netflix serve web traffic at 800Gb/s, including TSO, LRO, VM page cache zones, asynchronous sendfile and unmapped mbufs.

Aaron Boodman of Replicache asks why sync engines have not yet fixed web app complexity and what is missing for them to go mainstream. The talk lays out the ideas that led to the Zero sync engine.

Armin Ronacher, creator of Flask, explains how CPython's internals and C API leak into the language's semantics. Using examples like the complexity of the add operation, he shows why Python is hard to optimize or reimplement.

Rick Reed of WhatsApp explains at Erlang Factory 2014 how the service scaled to billions of messages with a very small engineering team. He covers the FreeBSD and Erlang stack, Mnesia usage, server counts and bottleneck work.

Casey Muratori's first refterm lecture lays out philosophies of optimization, distinguishing optimization from non-pessimization, which means avoiding needless work. It uses his fast terminal renderer project to show how fast computers really are.

Timothy Roscoe of ETH Zurich delivers the joint USENIX ATC/OSDI 2021 keynote arguing that operating systems must reckon with modern hardware, which is a heterogeneous collection of processors, firmware and coprocessors rather than a simple machine. It shows how much runs below and beside Linux.

Jim Keller gives a UC Berkeley EECS colloquium arguing that Moore's Law is not dead. He surveys upcoming technologies and the multiple innovation curves that can keep transistor density and performance scaling.

Chuck Moore, inventor of Forth, presents GreenArrays' 144-core asynchronous chip at Strange Loop 2013. He explains how idle cores draw almost no power and how tight code minimizes energy use.

Microsoft's Tony Chen explains how the Xbox One was designed to resist physical attacks, including secure boot, encrypted memory, a security processor and a hypervisor. The goal was to make any hardware attack cost more than the price of many games.

Herb Sutter's deep C++ and Beyond 2012 talk on atomics and the C++ memory model, covering why programmers chasing top performance need to understand hardware ordering. This is part one of two.

Dave Ackley demonstrates the Demon Horde Sort, an inherently robust sorting machine running in his Movable Feast Machine simulator. This is the uncut version with all details and side thoughts.

Bryan Cantrill of Oxide Computer Company gives a Stanford EE380 talk on rethinking the server. He argues that hyperscaler-style rack-scale machines with open firmware, RISC-V and Rust should be available to everyone, not just the giants.

Richard Feldman explains how pure functional languages can match or beat imperative ones on performance. Compilers can turn immutable code into in-place mutation, avoiding naive copying. The talk draws on his work on the Roc language.

Cliff Click of Azul Systems gives a Google Tech Talk on running Java business applications on a machine with about a thousand cores. He covers hardware and software codesign, including garbage collection hardware and the JIT.

A 2007 Google Tech Talk in which Cliff Click of Azul Systems presents a lock-free concurrent hash table that scales to 768 CPUs. He explains why it is correct by reasoning in a different way than usual happens-before and memory-order arguments.

Zach Tellman's Clojure West talk covers the basics of queueing theory and its practical use in systems, including backpressure, how queues break down under load, and pitfalls of naive core.async use.

Larry Hastings explains what Python's GIL is, what problems it solves and how it works, and presents his Gilectomy project to remove it, including the performance and C-extension obstacles.

Cliff Click, author of HotSpot's JIT compiler, shares hard-won advice for people writing virtual machines at the VMSS16 workshop. Topics include interpreters, JITs and performance lessons.

Simon Peyton Jones explains nested data parallelism and Data Parallel Haskell, an approach to exploiting multicore and distributed hardware while keeping a simple single-control-flow programming model.

Alex Russell's Chrome Dev Summit 2016 talk on building web experiences that work on slow, flaky networks and low-power devices. It argues developers should focus on the performance of real-world mobile hardware rather than desktop machines.

Emery Berger argues that performance is hard to measure and deliver on modern systems, showing how code layout and link order can swamp optimization effects. He presents tools that evaluate performance more reliably.

Khalil Estell's CppCon 2024 talk argues C++ exceptions can reduce binary size in firmware. He digs into how exceptions work and how to shrink their code footprint on embedded platforms.

Andrew Adams, a Halide developer, presents the Halide language for image processing and tensor computation. The talk explains the separation of algorithm from schedule with illustrated examples of parallelism, locality and redundancy tradeoffs.

The first part of Robert Baruch's series on building a 6800 CPU on an FPGA with nMigen, a Python-based hardware description language. It introduces the HDL while implementing a simpler 6800 core.

Casey Muratori follows up his refterm proof-of-concept, a GPU-based terminal renderer, with a second part covering memory usage, glyph sizing and correct Unicode and VT handling. It is built to show that a terminal can be fast and correct without heroic effort.

Chandler Carruth's CppCon 2016 talk tries to defuse the heated debate over undefined behavior in C and C++. He explains from the compiler writer's perspective why UB exists and how it enables optimization.

Christopher Domas presents research at DEF CON 26 showing a hidden alternate instruction set and undocumented hardware backdoor in some x86 processors, found on a third-party CPU. He uses it to ask how feasible wider hardware backdoors are.

Stephan T. Lavavej's CppCon 2019 talk on implementing floating-point to_chars and from_chars in Microsoft's C++ STL. It covers the history of float-string conversion and the algorithms that make it much faster.

Dave Ackley gives a high-level introduction to robust-first computing, which prioritizes robustness over efficiency in computer architecture. A sorting demo illustrates the idea.

Ian Cutress interviews chip architect Jim Keller about his time at AMD, Intel and elsewhere, management advice, design approach, Moore's Law and x86 versus Arm.

Armin Ronacher's EuroPython 2017 keynote examining how the CPython interpreter's leaky abstractions affect language design and how Python could evolve, drawing on JavaScript and Rust experience.

Jack Moffitt presents the architecture of Servo, Mozilla's experimental browser engine written in Rust, focusing on parallelism across cores, GPUs and SIMD and the safety properties gained from Rust.

A Google I/O 2013 talk by Android audio engineers on why reliable, low-latency audio is hard on the platform. It covers problem areas across the stack, platform work underway and techniques apps can use.

Matt Godbolt, creator of Compiler Explorer, tours surprising optimizations modern compilers perform, such as turning loops into closed-form sums and using popcount instructions. He explores what the compiler does behind the scenes.

Chris Lattner's ASPLOS 2021 keynote on the golden age of compiler design in an era of hardware and software co-design, covering compiler infrastructure for accelerators and unifying hardware IRs.

Simon Knowles, co-founder and CTO of Graphcore, talks about "intelligence processors", chips designed specifically for machine learning. The talk was given at the RAAIS 2017 summit and covers Graphcore's architecture.