pipelines

Gary Bernhardt's Cascadia Ruby Conference 2011 talk on using the Unix shell for practical problem solving. He builds pipelines interactively by iterative refinement, using small tools as levers.

R. Stanley Williams of HP Labs gives a keynote on the memristor, covering the physics, crossbar computation, and potential for memory and new computer architectures.

Casey Muratori's long talk arguing that modern software has ballooned to tens of millions of lines because of hardware and OS diversity. He proposes a stable ISA for entire system-on-a-chip packages and recalls when games shipped with their own boot disk.

Michael Steil's 33c3 talk explains essentially everything about the Game Boy: CPU, video hardware, peripherals, and the tricks used by games and demos. It revives the era of counting clock cycles around hardware limits.

Timothy Roscoe of ETH Zurich delivers the joint USENIX ATC/OSDI 2021 keynote arguing that operating systems must reckon with modern hardware, which is a heterogeneous collection of processors, firmware and coprocessors rather than a simple machine. It shows how much runs below and beside Linux.

Michael Steil and Christian Hessmann's 34C3 talk explaining the Apollo Guidance Computer end to end: hardware design, operating system, and mission software.

Jim Keller gives a UC Berkeley EECS colloquium arguing that Moore's Law is not dead. He surveys upcoming technologies and the multiple innovation curves that can keep transistor density and performance scaling.

Chuck Moore, inventor of Forth, presents GreenArrays' 144-core asynchronous chip at Strange Loop 2013. He explains how idle cores draw almost no power and how tight code minimizes energy use.

Christopher Domas presents at Black Hat 2017 how page fault analysis and processor fuzzing can exhaustively search the x86 instruction set. The talk uncovers undocumented instructions and hardware bugs and shows limits of disassemblers.

Microsoft's Tony Chen explains how the Xbox One was designed to resist physical attacks, including secure boot, encrypted memory, a security processor and a hypervisor. The goal was to make any hardware attack cost more than the price of many games.

Herb Sutter's deep C++ and Beyond 2012 talk on atomics and the C++ memory model, covering why programmers chasing top performance need to understand hardware ordering. This is part one of two.

Bryan Cantrill of Oxide Computer Company gives a Stanford EE380 talk on rethinking the server. He argues that hyperscaler-style rack-scale machines with open firmware, RISC-V and Rust should be available to everyone, not just the giants.

Cliff Click of Azul Systems gives a Google Tech Talk on running Java business applications on a machine with about a thousand cores. He covers hardware and software codesign, including garbage collection hardware and the JIT.

SpaceX engineers present at NVIDIA's GPU Technology Conference on a multi-physics code that simulates the full-scale Raptor methane engine. It covers GPU-based turbulent combustion modeling with adaptive grids and wavelet compression.

Simon Peyton Jones explains nested data parallelism and Data Parallel Haskell, an approach to exploiting multicore and distributed hardware while keeping a simple single-control-flow programming model.

PS5 lead system architect Mark Cerny gives a deep dive into the PS5's architecture, covering its SSD, I/O, audio and design goals. He explains how removing bottlenecks shapes future games.

Christopher Domas presents research at DEF CON 26 showing a hidden alternate instruction set and undocumented hardware backdoor in some x86 processors, found on a third-party CPU. He uses it to ask how feasible wider hardware backdoors are.

Chandler Carruth shows how to squeeze more performance out of already-optimized C++ code, covering how the CPU executes it. The talk goes into pipelining, branch prediction and speculative execution using benchmarks.

Dave Ackley gives a high-level introduction to robust-first computing, which prioritizes robustness over efficiency in computer architecture. A sorting demo illustrates the idea.

Scott Meyers explains how CPU caches work and why they matter for performance, covering cache levels, access speeds, associativity, and effects in multithreaded code. The focus is C++ and cache-aware, data-oriented programming.

Fedor Pikus's CppCon 2017 talk on C++ atomics, looking at what they let the programmer express and what the hardware actually does. It covers memory ordering and lock-free programming from basic to advanced.

Michael Steil's 25C3 talk covers the Commodore 64's architecture, quirks and demoscene tricks in about an hour. It aims to convey everything about the machine in a compact, nostalgic tour.

Michael Steil's 27c3 talk on reverse engineering the MOS 6502 from die shots into a transistor-level simulation, as in the Visual6502 project. It covers going from chip package to a digital model.

Chris Lattner's ASPLOS 2021 keynote on the golden age of compiler design in an era of hardware and software co-design, covering compiler infrastructure for accelerators and unifying hardware IRs.

Simon Knowles, co-founder and CTO of Graphcore, talks about "intelligence processors", chips designed specifically for machine learning. The talk was given at the RAAIS 2017 summit and covers Graphcore's architecture.

Cliff Click walks through a small performance example on a modern out-of-order CPU. He covers pipelining, ILP, CISC vs RISC, multicore, and why cache misses and the memory subsystem dominate performance.

Part two of Herb Sutter's C++ and Beyond 2012 session on atomic weapons, a deep dive into the C++ memory model, atomics, memory ordering, and hardware behavior. It ends with the modern meaning of volatile.

Christopher Domas's DEF CON 26 talk on secret processor registers that vendors reserve for third parties holding trusted keys. He examines how users are locked out of parts of their own CPUs.

Artem Dinaburg's DEF CON 19 talk on bit-squatting, where DRAM bit flips cause DNS requests to go to domains one bit off from the intended one. It shows how hardware faults can be exploited for hijacking without any software exploit.

Chris Celio of UC Berkeley compares the RISC-V, ARM and x86 instruction sets, with quantitative data on instruction counts and code density. It examines how the compressed extension fares against Thumb and x86.

Chuck Moore, creator of Forth, gives his annual Fireside Chat at Forth Day 2011 at Stanford. He talks about his multi-core GreenArrays chip design and demonstrates code running on it.

Bryan Cantrill's Scale By The Bay 2019 talk on software after Moore's Law. He covers the end of easy scaling and the move toward specialized, emerging architectures.

Bill Dally of NVIDIA gives a Hot Chips 2023 keynote on the challenges of building hardware for deep learning. He traces how GPUs have been adapted for machine learning, especially training.

Brian Troutwine's Code Mesh 2015 talk on the Apollo Guidance Computer. It covers the AGC's design, core rope memory, its interrupt and software behavior, and the pioneering engineering effort behind it.

Connor Krukosky, an 18-year-old college student and vintage computer collector, tells how he bought an IBM z890 mainframe and got it running at home. The talk was given at SHARE in San Antonio in March 2016.

Sophie Wilson, designer of the ARM instruction set, discusses the future of microprocessors, including the economics of scaling below 28nm and why much of a chip must stay powered off.

Christopher Domas's Black Hat talk demonstrates a hardware backdoor in a third-party x86 processor, a hidden core that grants root from userland. He uses it to discuss how feasible broader hardware backdoors might be.

A 36C3 talk on the AMD Platform Security Processor, an undocumented ARM core inside AMD CPUs that runs before the main processor. The speakers present their reverse engineering of its internals.

Joanna Rutkowska's 32C3 talk asks whether trustworthy client systems can be built on x86 hardware, and what realistically can be done about the challenges, such as Intel ME.

Seymour Cray's only surviving recorded talk, introducing the Cray-1 supercomputer in 1976. He describes the machine's design, including its vector architecture and cooling through the frame.