cpu

The second talk in the Mill CPU series by Mill Computing, covering the Belt, the Mill's operand-passing model that replaces general registers. It explains the cost of register renaming in conventional wide CPUs and how the Belt reaches high instruction-level parallelism.

A long Mill Computing lecture on the Mill CPU's compiler toolchain, covering the specializer that targets family members, scheduling and latency passes, and the belt. It explains how the compiler handles a wide-issue, exposed-pipeline design.

The first part of Robert Baruch's series on building a 6800 CPU on an FPGA with nMigen, a Python-based hardware description language. It introduces the HDL while implementing a simpler 6800 core.

A 36C3 talk on the AMD Platform Security Processor, an undocumented ARM core inside AMD CPUs that runs before the main processor. The speakers present their reverse engineering of its internals.

Cliff Click walks through a small performance example on a modern out-of-order CPU. He covers pipelining, ILP, CISC vs RISC, multicore, and why cache misses and the memory subsystem dominate performance.

Ian Cutress interviews Mike Clark, AMD's chief architect of Zen, about his career since the K5, how Zen began and how CPUs are designed. It also covers the future of AMD.

Christopher Domas presents research at DEF CON 26 showing a hidden alternate instruction set and undocumented hardware backdoor in some x86 processors, found on a third-party CPU. He uses it to ask how feasible wider hardware backdoors are.

Jim Keller gives a UC Berkeley EECS colloquium arguing that Moore's Law is not dead. He surveys upcoming technologies and the multiple innovation curves that can keep transistor density and performance scaling.

Christopher Domas's DEF CON 26 talk on secret processor registers that vendors reserve for third parties holding trusted keys. He examines how users are locked out of parts of their own CPUs.

Chuck Moore, creator of Forth, gives his annual Fireside Chat at Forth Day 2011 at Stanford. He talks about his multi-core GreenArrays chip design and demonstrates code running on it.

David Patterson's talk on the history of computer architecture, from RISC and superscalar designs to the end of Dennard scaling and Moore's Law. It argues that domain-specific architectures and open instruction sets open a new golden age.

Ian Cutress interviews chip architect Jim Keller about his time at AMD, Intel and elsewhere, management advice, design approach, Moore's Law and x86 versus Arm.

AdoredTV relays leaks and insider accounts of what it is like inside Intel, including staffing changes and morale. It is a commentary video from 2020.

An episode of Plogue's chipresearch series on emulating the Yamaha DX7 from the hardware up. It covers the sub CPU and main CPU, address map investigation, cartridges, firmware analysis and a skeleton MAME driver.

Der8auer tours Hetzner's test lab and shows a custom AM5 server motherboard with the CPU socket rotated 90 degrees, built for rack airflow in their AX52 servers.

Dragan Djuric presents Clojure libraries for GPU and numerical computing, including ClojureCL, ClojureCUDA and Neanderthal. He shows how a dynamic REPL workflow can be combined with low-level hardware acceleration for machine learning and data science.

Quentin Perret of Google gives a technical deep dive into protected KVM (pKVM) on Arm64, a confidential computing approach for CPUs without hardware extensions. It explains how the nVHE hypervisor manages stage-2 MMU access control to protect guest memory.

Jim Keller, CTO of Tenstorrent, talks at Samsung Foundry's SAFE 2021 about building AI silicon through modular, provable design. The talk also touches on Tenstorrent's RISC-V Ascalon core.

Timothy Roscoe of ETH Zurich delivers the joint USENIX ATC/OSDI 2021 keynote arguing that operating systems must reckon with modern hardware, which is a heterogeneous collection of processors, firmware and coprocessors rather than a simple machine. It shows how much runs below and beside Linux.

Chuck Moore, inventor of Forth, presents GreenArrays' 144-core asynchronous chip at Strange Loop 2013. He explains how idle cores draw almost no power and how tight code minimizes energy use.

Microsoft's Tony Chen explains how the Xbox One was designed to resist physical attacks, including secure boot, encrypted memory, a security processor and a hypervisor. The goal was to make any hardware attack cost more than the price of many games.

Herb Sutter's deep C++ and Beyond 2012 talk on atomics and the C++ memory model, covering why programmers chasing top performance need to understand hardware ordering. This is part one of two.

Dave Ackley demonstrates the Demon Horde Sort, an inherently robust sorting machine running in his Movable Feast Machine simulator. This is the uncut version with all details and side thoughts.

Bryan Cantrill of Oxide Computer Company gives a Stanford EE380 talk on rethinking the server. He argues that hyperscaler-style rack-scale machines with open firmware, RISC-V and Rust should be available to everyone, not just the giants.

Cliff Click of Azul Systems gives a Google Tech Talk on running Java business applications on a machine with about a thousand cores. He covers hardware and software codesign, including garbage collection hardware and the JIT.

Simon Peyton Jones explains nested data parallelism and Data Parallel Haskell, an approach to exploiting multicore and distributed hardware while keeping a simple single-control-flow programming model.

Dave Ackley gives a high-level introduction to robust-first computing, which prioritizes robustness over efficiency in computer architecture. A sorting demo illustrates the idea.

Chris Lattner's ASPLOS 2021 keynote on the golden age of compiler design in an era of hardware and software co-design, covering compiler infrastructure for accelerators and unifying hardware IRs.

Simon Knowles, co-founder and CTO of Graphcore, talks about "intelligence processors", chips designed specifically for machine learning. The talk was given at the RAAIS 2017 summit and covers Graphcore's architecture.

John Gustafson presents posits, a proposed drop-in replacement for IEEE 754 floats that is simpler in hardware and more flexible in precision. The seminar includes a live demo and machine learning results.

Part two of Herb Sutter's C++ and Beyond 2012 session on atomic weapons, a deep dive into the C++ memory model, atomics, memory ordering, and hardware behavior. It ends with the modern meaning of volatile.

A Computer History Museum oral history panel with four 3dfx founders on the company's rise with Voodoo Graphics and Glide, and its fall into bankruptcy. It runs about two and a half hours.

Artem Dinaburg's DEF CON 19 talk on bit-squatting, where DRAM bit flips cause DNS requests to go to domains one bit off from the intended one. It shows how hardware faults can be exploited for hijacking without any software exploit.

Dave Ackley presents robust-first computing and the ULAM programming language for the Movable Feast Machine, a cellular-automata-like architecture. It was a short video for the Future Programming Workshop 2015.

A Stanford EE380 seminar by Michael P. Frank of Sandia National Laboratories on generalized reversible computing. It surveys unconventional computing approaches as transistor scaling nears its limits and energy efficiency stops improving.

Chris Celio of UC Berkeley compares the RISC-V, ARM and x86 instruction sets, with quantitative data on instruction counts and code density. It examines how the compressed extension fares against Thumb and x86.

Bryan Cantrill's Scale By The Bay 2019 talk on software after Moore's Law. He covers the end of easy scaling and the move toward specialized, emerging architectures.

Bill Dally of NVIDIA gives a Hot Chips 2023 keynote on the challenges of building hardware for deep learning. He traces how GPUs have been adapted for machine learning, especially training.

A two-hour Oxide and Friends session answering questions after shipping the first Oxide rack. Topics include making hardware as a startup and why Oxide chose illumos.

Part two of a Computer History Museum oral history with Gary Davidian, covering his work on the 68000 emulator for PowerPC at Apple, Power Computing, clean-room contracting and later performance optimization work. It is nearly three hours long.